Certain embodiments of the inventive concept relate to clock generation circuits having a deskew function. Other embodiments of the inventive concept relate to semiconductor integrated circuit (IC) devices, such as a system-on-chip (SoC), memory device, or processor including a clock generation circuit having a deskew function.
Semiconductor ICs such as a SoC, processor, or memory device often require one or more clock signal(s). A clock divider may be used to divide the frequency of an input clock signal in order to generate a clock signal having a required frequency.
Unfortunately, the frequency division of a clock signal may introduce skew. Skew may be understood as a difference between a desired clock signal arrival time (e.g., a clock transition, a rising clock edge, a falling clock edge, etc.) and an actual clock signal arrival time. And clock dividers are often characterized by large latency periods and poor jitter characteristics. Accordingly, a deskew circuit is often required to improve jitter characteristics by eliminating or reducing clock signal skew. It is therefore typical to provide a deskew circuit together with a clock divider. Unfortunately, the circuitry necessary to deskew both rising and falling edges of a clock signal currently requires a great many constituent elements (e.g., flip-flops) and is highly complex in its design and operation.